FIG. 1 illustrates a prior art embodiment of a master-slave latch system 20. The master-slave latch system includes a master latch portion 22 and a slave latch portion 24. A logic portion 26 provides both an input 28 and a complementary input 30 (if input 28 is HIGH, then complementary input 30 is LOW, and vice versa) to the master latch portion 22. The master latch portion 22 has an output 32, and a complementary output 34, both of which are input to the slave latch portion 24 as illustrated. The slave latch portion 24 has an output 36 and a complementary output 38, both of which represent an output of the master-slave latch system 20.
The master latch portion 22 has a complementary write or clock segment 40 and cross-coupled latch segment 44. The complementary write segment contains an n-channel transistor n1 which selectively connects the remainder of the complementary write segment 40 to ground, as well as n-channel transistors n2 and n3. The cross-coupled latch segment contains n-channel transistors n5 and n6, as well as p-channel transistors p1 and p2, combined in a well known manner.
The slave latch portion 24 has a complementary write segment 48 and a cross-coupled latch segment 52. The complementary write segment contains an n-channel transistor n7 which selectively connects the remainder of the complementary write segment 48 to ground, and n-channel transistors n8 and n9. The cross-coupled latch segment 52 contains n-channel transistors n10 and n11, as well as p-channel transistors p3 and p4. The transistors in the master latch portion 22 and the slave latch portion 24 are electrically connected as illustrated in FIG. 1.
FIG. 2 illustrates a sample clock input including a master clock input .PHI..sub.m and a slave clock input .PHI..sub.s. The master clock input .PHI..sub.m and the slave clock input .PHI..sub.s are input at the location referred to in FIG. 1. When the master clock input .PHI..sub.m goes high, the n-channel transistor n1 is turned on, and a high level of electric current is permitted to flow through it. Turning the n-channel transistor n1 on permits effective operation of the n-channel transistors n2 and n3, such that the values of the input 28 and the complementary input 30 can be read into the master latch portion 22, thereby enabling the master latch portion 22. Assume that initially node 60 of the master latch is at full Vdd level (node 62 will be at ground level), and a new data from logic circuits results in input 28 being at a high level (input 30 is at a low level). With master clock input .PHI..sub.m turning on, the voltage at node 60 (which is connected to output 32) starts to drop below a level equivalent to V.sub.DD -V.sub.(threshold) then p-channel transistor p2 starts to turn on, and n-channel transistor n6 starts to turn off. Consequently, node 62 is being charged toward V.sub.DD level.
When the voltage at node 62 is raised to a high level as described in the prior paragraph, then the p-channel transistor p1 will be turned off and the n-channel transistor n5 will be turned on, the combination of which will tend to drive the voltage at node 60 to ground. As the process outlined in the above two paragraphs continues, then the voltage difference between nodes 60 and 62 increases until a voltage difference value of V.sub.DD is reached. This process will continue even after the master clock input .PHI..sub.m goes low. However, if the polarity between the input 28 and the complementary input 30 changes prior to the master clock input .PHI..sub.m going low, then the relative polarities at nodes 60 and 62 will also be reversed. After the master clock input .PHI..sub.m goes low, it can be assumed that the voltage at nodes 60 and 62 will remain in the same contention state as it was in when the clock input initially dropped. Therefore, the master latch portion 22 functions as a static latch, as does the slave latch portion 24.
For proper operation of the master-slave latch system 20 of FIG. 1, whenever the master clock input .PHI..sub.m is high (thereby enabling the master latch portion 22), the slave clock input .PHI..sub.s should be low (thereby dis-enabling the slave latch portion 24). This limits the voltages of the slave latch portion 24 affecting any of the voltages in the master latch portion 22. An operational timing sequence between the master clock input .PHI..sub.m and the slave clock input .PHI..sub.s is illustrated in FIG. 2. Only one of the two clock inputs is high at any given time.
After the master clock input .PHI..sub.m goes low, the voltage at the slave clock input .PHI..sub.s in FIG. 1 goes high. The structure of the slave latch portion 24 is identical to that of the master latch portion 22; and the operation is functions the same for each respective circuit element or portion. Using logic similar what was previously described with respect to the master latch portion, as soon as the master clock input .PHI..sub.m goes low while the voltage at the slave clock input .PHI..sub.s goes high, then the values of the output 32, and the complementary output 34, will be read directly into the slave latch portion 24 at nodes 33 and 35, respectively. The slave latch portion 24 functions as a static latch.
One disadvantage of the configuration illustrated in FIG. 2, is that in a large circuit formed from a large number of master-slave latch systems 20, the time required for a signal to travel from where the signal is produced (at an actuator--not illustrated) to any of the distinct master-slave latch systems can vary based upon a variety of factors including the distance therebetween; the material of the connection to the system; etc. This difference in time At that is required for a signal to travel from the actuator to the different master-slave latch systems 20 results in what is known as clock skew. The clock skew is undesirable because it limits the ability to precisely determine or control the time of a raising edge or a falling edge for each of the master clock input .PHI..sub.m and the slave clock input .PHI..sub.s. Because of this uncertainty, the rate of clock signal reversals between the master clock input .PHI..sub.m and the slave clock input .PHI..sub.s cannot be performed as quickly as is the case if the precise time of falling edge or raising edge in both of the clocks could be precisely determined.
In a high speed microprocessor, the reliable control of clock skew and distribution becomes more stringent and difficult. The cycle time reduction due to clock skew directly decreases the useful time permitted for logic operations. The clock skew comes from the mis-match of on-chip clock buffers distributed within the chip. In conventional level sensitive scan design (hereinafter referred to as "LSSD") using master latch portions and slave latch portions as illustrated in FIG. 1, multi-phase clocks with specific phase relations are required for proper operation. The relative phase requirement, such as requiring non-overlapping clocks, further increases the complexity associated with limiting clock skew.
In the article "Multigigahertz CMOS Dual-Modulus Prescalar IC", Cong et al., IEEE Journal of Solid State Circuits, October 1988, a low-power CMOS dual modulus IC is described. A Nand gate which feeds into a single flip-flop is illustrated. Both the flip-flop and the nand gate are controlled by a single clock. There is no teaching in the Cong et al. article of utilizing a single clock to control both master and slave latches.
U.S. Pat. No. 5,036,217, which issued Jul. 30, 1991 to Rollins et al. discloses a high speed dynamic flip-flop device. Dynamic systems are intended to function relatively quickly using relatively little energy consumption. However, dynamic systems in general suffer from contention problems when left at a single state for relatively long periods. The present invention relates to static latches, in general.
Recently, high speed CMOS microprocessors have been configured with a clock speed of 200 MHz. The use of a single phase clock has the capability of greatly simplifying the distribution of the clock signal across a chip, and reduce the associated clock skew. Reducing clock skew may be accomplished by applying a single clock to both the master and slave latches, thereby eliminating uncertainty about clock timing between the master and slave latches. However, in order to be able to operate a microprocessor with a single clock phase, special latches are required for proper operation. In an LSSD design, it would be highly desirable to be able to use a single phase clock to be able to operate a master/slave latch configuration. In addition, it would be desirable to be able to test a master/slave latch configuration; which is operated by a single phase clock using a scan process.
It is desirable to be able to have a great deal of certainty about when the relative timing of the falling edge and/or the rising edge of both the master clock input .PHI..sub.m and the slave clock input .PHI..sub.s is. One technique to accomplish this is to provide a single phase clock which controls both the master clock input .PHI..sub.m and the slave clock input .PHI..sub.s. It would also be highly desirable to be able to provide an efficient scanning technique for the master-slave latch system which utilizes a single phase clock.